A central processing unit (CPU), as a processor, has cache memories realized by a random access memory (RAM). The cache memories are used in a hierarchy of different sizes, for example, an L1 (Level 1: primary) cache memory and L2 (Level 2: secondary) cache memory. Further, the L2 cache memory includes the content of the L1 cache memory.
A cache memory consumes less power consumption the fewer the number of memory cells in the RAM accessed, so by storing frequently accessed data in a cache memory closer to the CPU core or other processor, it is possible to lower the power consumption of the cache memories overall.
A cache memory has been proposed having a data array for storing data, a tag array for storing tags relating to the data, and a comparator comparing a tag address as a physical address read out from the tag array and a tag address as a physical address requested to be read out from the outside. The tag array reads out tag addresses from the memory cells associated with an index address. When a tag address read out from the tag array and a tag array requested to be read out from the outside match, the comparator outputs a “cache hit” signal to the data array. The data array reads out the data from the memory cells specified by the index address after receiving a cache hit signal.
In this way, the cache memory searches through the tag array for a tag address corresponding to the index address and reads out the data from the data array only when there is a cache hit, that is, a match of a tag address included in the memory access request and a tag address read out from the tag memory. Therefore, when a cache miss occurs, data is not read out from the data array, so the power consumed for operating the data array can be suppressed.
Further, a cache memory has been proposed having a modify address storage unit for storing the addresses of written over data and cache memory blocks of predetermined ranges of addresses included in the cache memory. When a cache miss occurs in a data access operation from the processing unit, the cache memory determines a block to be evicted or purged from the cache memory based on a predetermined algorithm and searches for written over data in the block concerned with reference to the modify address storage unit. If there is written over data, the cache memory writes the written over data in the main memory and writes the data to be read from the main memory in the cache memory.
By selectively writing back the written over data in the main memory in this way, the wasteful operation of the cache memory writing data not written over in the cache memory back into the main memory when there is no need for writing it back can be eliminated.
[Patent Document 1] Japanese Laid-open Patent Publication No. 2003-150446
[Patent Document 2] Japanese Laid-open Patent Publication No. 4-273549